ASIC/FPGA Verification Engineer
|
Elektro
Gliwice
junior specialist (Junior), specialist (Mid / Regular) - work on projects for the largest players in ASIC world, - verify digital circuits using SystemVerilog language and the most modern ASIC verification methodology - UVM, - work on a structured and well planned projects (we use Requirements Based Development Processes in our projects). Our requirements - at least 2-3 years of relevant... |
Zobacz zarobki & Więcej info |
|
jeden dzień temu
|
|